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| 1 MX25L1633E datasheet MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013
2 contents features ................................................................................................................................................. 5 general..............................................................................................................................................................5 performance ............ .......................................................................................................................................... 5 software features ............................................................................................................................................. 5 hardware features............................................................................................................................................6 general description ........................................................................................................................ 7 table 1. additional feature comparison ........................................................................................................... 7 pin configurations ............................................................................................................................ 8 pin description ..................................................................................................................................... 8 block diagram ...................................................................................................................................... 9 da ta protection ................................................................................................................................. 10 table 2. protected area sizes ......................................................................................................................... 11 t able 3. 512-bit secured otp defnition ............ ............................................................................................. 11 memory organization .............................................................................................................................. 12 table 4. memory organization ....................................................................................................................... 12 device operation ............................................................................................................................... 13 figure 1. serial modes supported...................................................................................................................13 command description ...................................................................................................................... 14 table 5. command set .................................................................................................................................... 14 (1) write enable (wren) ................................................................................................................................ 15 (2) write disable (wrdi) ............ ..................................................................................................................... 15 (3) read identifcation (rdid) ......................................................................................................................... 15 (4) read status register (rdsr) ........... ........................................................................................................ 16 status register ................................................................................................................................................ 16 (5) write status register (wrsr) ............ ....................................................................................................... 17 table 6. protection modes ............................................................................................................................... 17 (6) read data bytes (read) .......................................................................................................................... 18 (7) read data bytes at higher speed (fast_read) .................................................................................... 18 (8) 2 x i/o read mode (2read) ........... .......................................................................................................... 18 (9) 4 x i/o read mode (4read) ........... .......................................................................................................... 19 (10) sector erase (se) .................................................................................................................................... 19 (11) block erase (be) ...................................................................................................................................... 20 (12) chip erase (ce) ....................................................................................................................................... 20 (13) page program (pp)..................................................................................................................................20 (14) 4 x i/o page program (4pp) .................................................................................................................... 21 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 3 (15) deep power-down (dp) ........................................................................................................................... 21 (16) release from deep power-down (rdp), read electronic signature (res) ........................................... 21 (17) read electronic manufacturer id & device id (rems), (rems2), (rems4) ........... .............................. 22 table 7. id defnitions .................................................................................................................................... 22 (18) enter secured otp (enso) .................................................................................................................... 22 (19) exit secured otp (exso) ....................................................................................................................... 23 (20) read security register (rdscur) ......................................................................................................... 23 table 8. security register defnition ............................................................................................................... 23 (21) write security register (wrscur) ......................................................................................................... 23 power-on state .................................................................................................................................. 24 electrical specifications ............................................................................................................. 25 absolute maximum ratings ............................................................................................................................25 figure 2. maximum negative overshoot waveform ....................................................................................... 25 capacitance .................................................................................................................................................... 25 figure 3. maximum positive overshoot waveform ........... .............................................................................. 25 figure 4. input test waveforms and measurement level ............ ................................................................... 26 figure 5. output loading.................................................................................................................................26 table 9. dc characteristics ............................................................................................................................. 27 table 10. ac characteristics ........................................................................................................................... 28 timing analysis ....................................................................................................................................... 29 figure 6. serial input timing ........................................................................................................................... 29 figure 7. output timing ................................................................................................................................... 29 figure 8. wp# setup timing and hold timing during wrsr when srwd=1 ................................................ 30 figure 9. write enable (wren) sequence (command 06) ............................................................................ 30 figure 10. write disable (wrdi) sequence (command 04) ............ ............................................................... 30 figure 11. read identifcation (rdid) sequence (command 9f) ................................................................... 31 figure 12. read status register (rdsr) sequence (command 05) ........... .................................................. 31 figure 13. write status register (wrsr) sequence (command 01) ............ ................................................ 31 figure 14. read data bytes (read) sequence (command 03) ................................................................... 32 figure 15. read at higher speed (fast_read) sequence (command 0b) ........... .................................... 32 figure 16. 2 x i/o read mode sequence (command bb) .............................................................................. 33 figure 17. 4 x i/o read mode sequence (command eb) .............................................................................. 33 figure 18. 4 x i/o read enhance performance mode sequence (command eb) ............ .............................. 34 figure 19. page program (pp) sequence (command 02).............................................................................35 figure 20. 4 x i/o page program (4pp) sequence (command 38) ............ ................................................... 35 figure 21. sector erase (se) sequence (command 20) ............................................................................... 36 figure 22. block erase (be) sequence (command d8) ................................................................................ 36 figure 23. chip erase (ce) sequence (command 60 or c7) ........................................................................ 36 figure 24. deep power-down (dp) sequence (command b9)......................................................................37 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 4 figure 25. rdp and read electronic signature (res) sequence (command ab) ....................................... 37 figure 26. release from deep power-down (rdp) sequence (command ab) ............................................ 38 figure 27. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df) ....... 38 figure 28. power-up timing ............................................................................................................................ 39 table 11. power-up timing ............................................................................................................................. 39 initial delivery state.........................................................................................................................................39 operating conditions ...................................................................................................................... 40 figure 29. ac timing at device power-up ...................................................................................................... 40 figure 30. power-down sequence ................................................................................................................. 41 erase and programming performance ................................................................................... 42 data retention .................................................................................................................................. 42 latch-up characteristics ............................................................................................................. 42 ordering informa tion ..................................................................................................................... 43 part name description .................................................................................................................... 44 package information ....................................................................................................................... 45 revision history ................................................................................................................................ 48 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 5 16m-bit [x 1/x 2/x 4] cmos mxsmio ? (serial multi i/o) flash memory features general 6huldo3hulskhudo,qwhuidfhfrpsdwleoh0rghdqg0rgh ? 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two i/o read mode) structure or 4,194,304 x 4 bits (four i/o read mode) structure (txdo6hfwruzlw.ewhhdf - any sector can be erased individually (txdoorfnzlw.ewhhdf - any block can be erased individually 6lqjoh3rzhu6xsso2shudwlrq - 2.7 to 3.6 volt for read, erase, and program operations /dwfxssurwhfwhgwrp iurp9wr9ff9 performance lk3huirupdqfh - fast read - 1 i/o: 104mhz with 8 dummy cycles - 2 i/o: 85mhz with 4 dummy cycles - 4 i/o: 85mhz with 6 dummy cycles - fast access time: 104mhz serial clock - serial clock of four i/o read mode : 85mhz, which is equivalent to 340mhz - fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 9us (typical) )dwhudhwlphpwshfwru.ewhshuhfwruwseorfn.ewhshueorfnwsfls /rz3rzhu&rqxpswlrq - low active read current: 25ma(max.) at 104mhz and 10ma(max.) at 33mhz - low active programming current: 15ma (typ.) - low active sector erase current: 9ma (typ.) - low standby current: 15ua (typ.) 7 slfdohudhsurjudpffoh hduvgdwduhwhqwlrq software features ,qsxwdwd)rupdw - 1-byte command code gdqfhg6hfxulw)hdwxuh - block lock protection 7h 33 wdwx elw ghqh wh l]h ri wh duhd wr eh riwzduh surwhfwlrq djdlqw surjudp dqg hudh instructions gglwlrqdoelwhfxuhg273iruxqltxhlghqwlhu xwr(udhdqg xwr3urjudpojrulwp xwrpdwlfdoohudhdqghulhgdwddwhohfwhghfwru xwrpdwlfdoosurjudpdqghulhgdwddwhohfwhgsdjhedqlqwhuqdodojrulwpwdwdxwrpdwlfdoowlphwh surjudpsxohzlgwqsdjhwrehsurjudphgrxogdhsdjhlqwhhudhgwdwhuw ? status register feature ? lectronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - both rems,rems2 and rems4 commands for 1-byte manufacturer id and 1-byte device id MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 6 hardware features ? sc inut - serial clock input 6,6,2 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode 626,2 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode :36,2 - hardware write protection or serial data input/output for 4 x i/o read mode 1&6,2 - nc pin or serial data input/output for 4 x i/o read mode 3 &.( - 8-land wson (6x5mm) - 8-land uson (4x4mm) - 8-pin sop (200mil) - all devices are rohs compliant & halogen-free. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 7 table 1. additional feature comparison general description the MX25L1633E are 16,777,216 bit serial flash memory, which is confgured as 2,097,152 x 8 internally. when it is in two or four i/o read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. the MX25L1633E feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits in - put and data output. when it is in four i/o read mode, the si pin, so pin, wp# pin and nc pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the MX25L1633E provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, and erase command is executes on sector (4k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the MX25L1633E utilizes macronix proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. additional features part name protection and security read performance identifer flexible block protection (bp0- bp3) 512-bit secured otp 2 i/o read 4 i/o read res (command: ab hex) rems (command: 90 hex) rems2 (command: ef hex) rems4 (command: df hex) rdid (command: 9f hex) MX25L1633E v v v v 24 (hex) c2 24 (hex) (if add=0) c2 24 (hex) (if add=0) c2 24 (hex) (if add=0) c2 24 15 (hex) mx25l1635d v v v v 24 (hex) c2 24 (hex) (if add=0) c2 24 (hex) (if add=0) c2 24 (hex) (if add=0) c2 24 15 (hex) MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 8 pin configurations pin description 8-land wson (6x5mm), uson (4x4mm) 8-pin sop (200mil) symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o read mode) nc/sio3 nc pin (not connect) or serial data input & output (for 4xi/o read mode) vcc + 3.3v power supply gnd ground 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc nc/sio3 sclk si/sio0 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc nc/sio3 sclk si/sio0 8 7 6 5 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 9 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 nc/sio3 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 10 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or pro - gramming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command se - quences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? v alid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? w rite enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - w rite disable (wrdi) command completion - w rite status register (wrsr) command completion - page program (pp , 4pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) comma nd completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). ? advanced security features: there are some protection and securuity features which protect content from inad - vertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the proected area defnition is shown as table of "protected area sizes", the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware proteced mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and srwd bit. if the system goes into four i/o read mode, the feature of hpm will be disabled. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 11 ii. additional 512-bit secured otp for unique identifer: to provide 512-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. please refer to table 3. 512-bit secured otp defnition . - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 512-bit secured otp by entering 512-bit secured otp mode (with enso command), and go - ing through normal program procedure, and then exiting 512-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register defnition" for security register bit defnition and table of "512-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 512-bit se - cured otp mode, array access is not allowed. table 3. 512-bit secured otp defnition table 2. protected area sizes address range size standard factory lock customer lock xxxx00~xxxx0f 128-bit esn (electrical serial number) determined by customer xxxx10~xxxx3f 384-bit n/a status bit protect level bp3 bp2 bp1 bp0 16mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, protected block 31th) 0 0 1 0 2 (2blocks, protected block 30th-31th) 0 0 1 1 3 (4blocks, protected block 28th-31th) 0 1 0 0 4 (8blocks, protected block 24th-31th) 0 1 0 1 5 (16blocks, protected block 16th-31th) 0 1 1 0 6 (32blocks, protected all) 0 1 1 1 7 (32blocks, protected all) 1 0 0 0 8 (32blocks, protected all) 1 0 0 1 9 (32blocks, protected all) 1 0 1 0 10 (16blocks, protected block 0th-15th) 1 0 1 1 11 (24blocks, protected block 0th-23th) 1 1 0 0 12 (28blocks, protected block 0th-27th) 1 1 0 1 13 (30blocks, protected block 0th-29th) 1 1 1 0 14 (31blocks, protected block 0th-30th) 1 1 1 1 15 (32blocks, protected all) MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 12 table 4. memory organization memory organization block sector address range 31 511 1ff000h 1fffffh : : : 496 1f0000h 1f0fffh 30 495 1ef000h 1effffh : : : 480 1e0000h 1e0fffh 29 479 1df000h 1dffffh : : : 464 1d0000h 1d0fffh 28 463 1cf000h 1cffffh : : : 448 1c0000h 1c0fffh 27 447 1bf000h 1bffffh : : : 432 1b0000h 1b0fffh 26 431 1af000h 1affffh : : : 416 1a0000h 1a0fffh 25 415 19f000h 19ffffh : : : 400 190000h 190fffh 24 399 18f000h 18ffffh : : : 384 180000h 180fffh 23 383 17f000h 17ffffh : : : 368 170000h 170fffh 22 367 16f000h 16ffffh : : : 352 160000h 160fffh 21 351 15f000h 15ffffh : : : 336 150000h 150fffh 20 335 14f000h 14ffffh : : : 320 140000h 140fffh 19 319 13f000h 13ffffh : : : 304 130000h 130fffh 18 303 12f000h 12ffffh : : : 288 120000h 120fffh 17 287 11f000h 11ffffh : : : 272 110000h 110fffh 16 271 10f000h 10ffffh : : : 256 100000h 100fffh block sector address range 15 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh 14 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 13 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, all so pins of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1. 5. for the following instructions: rdid, rdsr, rdscur, read, f ast_read, 2read, 4read, res, rems, rems2, and rems4 the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, 4pp, rdp, dp, enso, exso,and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of w rite status register, program, erase operation, to access the memory array is neglect - ed and not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, -cpol=1 for sclk high while idle, -cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 14 command description table 5. command set command (byte) wren (write enable) wrdi (write disable) rdid (read identifc- ation) rdsr (read status register) wrsr (write status register) read (read data) fast read (fast read data) 2read (2 x i/o read command) note1 4read (4 x i/o read command) note2 1st byte 06 (hex) 04 (hex) 9f (hex) 05 (hex) 01 (hex) 03 (hex) 0b (hex) bb (hex) eb (hex) 2nd byte values ad1 (a23-a16) ad1 add(2) add(4) & dummy(4) 3rd byte ad2 (a15-a8) ad2 add(2) & dummy(2) dummy(4) 4th byte ad3 (a7-a0) ad3 5th byte dummy action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs jedec id: 1-byte manufact- urer id & 2-byte device id to read out the values of the status register to write new values of the status register n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by 2 x i/o until cs# goes high n bytes read out by 4 x i/o until cs# goes high command (byte) 4pp (quad page program) se (sector erase) be (block erase) ce (chip erase) pp (page program) dp (deep power down) rdp (release from deep power down) res (read electronic id) 1st byte 38 (hex) 20 (hex) d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) ab (hex) 2nd byte ad1 ad1 ad1 ad1 x 3rd byte ad2 ad2 ad2 x 4th byte ad3 ad3 ad3 x action quad input to program the selected page to erase the selected sector to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode to read out 1-byte device id command (byte) release read enhanced rems (read electronic manufacturer & device id) rems2 (read id for 2x i/o mode) rems4 (read id for 4x i/o mode) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) 1st byte ffh (hex) 90 (hex) ef (hex) df (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) 2nd byte x x x x 3rd byte x x x x 4th byte x add (note 3) add (note 3) add (note 3) action all these commands ffh, 00h, aah or 55h will escape the performance enhance mode output the manufacturer id & device id output the manufacturer id & device id output the manufacturer id & device id to enter the 512-bit secured otp mode to exit the 512-bit secured otp mode to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be update) note 1: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. note 2: the count base is 4-bit for add(4) and dummy(4) because of 4 x i/o. note 3: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 4: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 15 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction codecs# goes high. (see figure 9) (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. (see figure 10 ) the wel bit is reset by following situations: - power-up - w rite disable (wrdi) instruction completion - w rite status register (wrsr) instruction completion - page program (pp) instruction completion - quad page program (4pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion (3) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id is c2(hex), the memory type id is 24(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of "id defnitions". (see table 7) the sequence of issuing rdid instruction is: cs# goes lowsending rdid instruction code24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. (see figure 11 .) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 16 (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes lowsending rdsr instruction codestatus register data out on so (see figure 12 ) the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is applied to a protected memory area. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area(as defned in table 2 ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruc - tion to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruc - tion can be executed). qe bit. the quad enable (qe) bit, non-volatile bit, performs quad when it is reset to "0" (factory default) to enable wp# or is set to "1" to enable quad sio2 and sio3. srwd bit. the status register write disable (srwd) bit, non-volatile bit, which is set to "0" (factory default). the srwd bit is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protec - tion mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. status register note 1: see the table 2 " protected area size". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 17 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the pro - tected area of memory (as shown in table 2 ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the statur register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes lowsending wrsr instruction codestatus register data on si cs# goes high. (see figure 13 ) the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 6. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 2 . as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when sr wd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0 and qe. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when sr wd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0 and qe. the protected area, which is defned by bp3, bp2, bp1, bp0, is at soft - ware protected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when sr wd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3, qe bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3, qe of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 18 note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system goes into four i/o read mode, the feature of hpm will be disabled. (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address can be at any location. the address is auto - matically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code 3-byte address on sidata out on soto end read operation can use cs# to high at any time during data out. (see figure 14 ) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes lowsending fast_read instruction code 3-byte address on si1-dummy byte address on sidata out on so to end fast_read operation can use cs# to high at any time during data out. (see figure 15 ) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (8) 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address can be at any location. the address is automatically increased to the next high - er address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address inter - leave on sio1 & sio0 4 dummy cycles on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (see figure 16 for 2 x i/o read mode timing waveform). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 19 (9) 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address can be at any location. the address is automatically increased to the next higher address af - ter each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address inter - leave on sio3, sio2, sio1 & sio0 6 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out (see figure 17 for 4 x i/o read mode timing waveform). another sequence of issuing 4 read instruction especially useful in random access is : cs# goes low sending 4 read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out interleave on sio3, sio2, sio1 and sio0 till cs# goes high cs# goes low (reduce 4 read instruction) 24-bit random access address (see figure 18 for 4x i/o read enhance performance mode timing waveform). in the performance-enhancing mode (note of figure. 18 ), p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h,5ah,f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h. and afterwards cs# is raised or issuing ff com - mand (cs# goes high cs# goes lowsending 0xffcs# goes high) instead of no toggling, the system then will escape from performance enhance mode and return to normal opertaion. in these cases, tshsl=15ns(min) will be specifed. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. (10) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 3 ) is a valid address for sector erase (se) in- struction. the cs# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes lowsending se instruction code3-byte address on si cs# goes high. (see figure 21) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 20 (11) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 3 ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the eighth bit of address byte been latched- in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code3-byte address on si cs# goes high. (see figure 22 ) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the page. (12) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary (the eighth bit of instruction code been latched-in), otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. (see fig- ure 23) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". (13) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes lowsending pp instruction code3-byte address on si at least 1-byte on data on si cs# goes high. (see figure 19 ) the cs# must be kept to low during the whole page program instr uction cycle; the cs# must go high exactly at the byte boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex - ecuted. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 21 progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. (14) 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 85mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we sug - gest that while executing this command (especially during sending data), user can slow the clock speed down to 85mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes lowsending 4pp instruction code3-byte address on sio[3:0] at least 1-byte on data on sio[3:0] cs# goes high. (see figure 20) (15) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not ac - tive and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction code cs# goes high. (see fig- ure 24) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction (those instructions allow the id being reading out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not exec uted. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. (16) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 10. ac characteristics . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions in next page. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. the sequence is shown as figure 25 and figure 26 . even in deep power-down mode, the rdp and res are also MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 22 allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. (17) read electronic manufacturer id & device id (rems), (rems2), (rems4) the rems, rems2 & rems4 instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems4 instruction is rec - ommended to use for 4 i/o identifcation and rems2 instruction is recommended to use for 2 i/o identifcation. the rems, rems2 & rems4 instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" or "efh" or "dfh" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 27. the device id values are listed in table 7 of id defnitions in next page. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 7. id defnitions (18) enter secured otp (enso) the enso instruction is for entering the additional 512-bit secured otp mode. the additional 512-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes lowsending enso instruction to enter secured otp mode cs# goes high. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once se- curity otp is lock down, only read related commands are valid. rdid command manufacturer id memory type memory density c2 24 15 res command electronic id 24 rems/rems2/rems4/ command manufacturer id device id c2 24 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 23 table 8. security register defnition (21) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 512-bit secured otp area. once the ldso bit is set to "1", the se - cured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes lowsending wrscur instructioncs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. (19) exit secured otp (exso) the exso instruction is for exiting the additional 512-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes lowsending exso instruction to exit secured otp modecs# goes high. (20) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low sending rdscur instruction security regis - ter data out on socs# goes high. the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for custom - er lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 512-bit secured otp area cannot be update any more. while it is in 512-bit secured otp mode, main array access is not allowed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x ldso (indicate if lock-down secured otp indicator bit reserved reserved reserved reserved reserved reserved 0 = not lock-down 1 = lock-down (cannot program/erase otp) 0 = non-factory lock 1 = factory lock volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 24 power-on state the device is at below states when power-up: - standby mode ( please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the fgure of " power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 25 notice: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3 . during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 2, and figure 3. absolute maximum ratings electrical specifications capacitance figure 2. maximum negative overshoot waveform figure 3. maximum positive overshoot waveform rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns ta = 25c, f = 1.0 mhz MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 26 figure 4. input test waveforms and measurement level figure 5. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf including jig capacitance MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 27 table 9. dc characteristics notes : 1. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 15 25 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 2 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 25 ma f=104mhz, fq=85mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 20 ma ft=85mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 15 20 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 3 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 9 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 15 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 28 table 10. ac characteristics notes: 1. tch + tcl must be greater than or equal to 1/ f (fc or fr). 2. v alue guaranteed by characterization, not 100% tested in production. 3. tshsl=15ns from read instruction, tshsl=50ns from write/erase/program instruction. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as figure 4 and figure 5. symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz fpsclk fp clock frequency for pp instructions d.c. 86 mhz f4p clock frequency for 4pp instructions d.c. 85 mhz frsclk fr clock frequency for read instructions 33 mhz ftsclk ft clock frequency for 2read instructions 85 mhz fq clock frequency for 4read instructions 85 mhz tch(1) tclh clock high time (1633e-10g) fc=104mhz 4.7 ns fr=33mhz 13 ns tcl(1) tcll clock low time (1633e-10g) fc=104mhz 4.7 ns fr=33mhz 13 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl(3) tcsh cs# deselect time read 15 ns write/erase/program 50 ns tshqz(2) tdis output disable time 2.7v-3.6v 10 ns 3.0v-3.6v 8 ns tclqv tv clock low to output valid loading: 30pf/15pf 2.7v-3.6v 9/8 ns 3.0v-3.6v 8/6 ns tclqx tho output hold time 1 ns twhsl write protect setup time 20 ns tshwl write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 8.8 us tres2(2) cs# high to standby mode with electronic signature read 8.8 us tw write status register cycle time 40 100 ms tbp byte-program 9 50 us tpp page program cycle time 0.6 3 ms tse sector erase cycle time 40 200 ms tbe block erase cycle time 0.4 2 s tce chip erase cycle time 5 20 s temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 29 figure 6. serial input timing figure 7. output timing timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 30 figure 8. wp# setup timing and hold timing during wrsr when srwd=1 figure 9. write enable (wren) sequence (command 06) figure 10. write disable (wrdi) sequence (command 04) high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so 21 34567 high-z 0 06 command sclk si cs# so 21 34567 high-z 0 04 command sclk si cs# so MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 31 figure 11. read identifcation (rdid) sequence (command 9f) figure 12. read status register (rdsr) sequence (command 05) figure 13. write status register (wrsr) sequence (command 01) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 32 figure 14. read data bytes (read) sequence (command 03) figure 15. read at higher speed (fast_read) sequence (command 0b) sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 configurable dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0b command MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 33 figure 17. 4 x i/o read mode sequence (command eb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 eb(hex) address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output notes: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. figure 16. 2 x i/o read mode sequence (command bb) note: 1. si/sio0 or so/sio1 should be kept "00" or "11" in the frst 2 dummy cycles. in other words, p2=p0 or p3=p1 is necessary. high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bb(hex) p2 p0 address bit22, bit20, bit18...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 p3 p1 8 bit instruction 12 bit address 4 dummy cycle data output MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 34 figure 18. 4 x i/o read enhance performance mode sequence (command eb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 eb(hex) address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output sclk note: performance enhance mode, if p7=p3 & p6=p2 & p5=p1 & p4=p0 (toggling), ex: a5, 5a, 0f reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles 4 dummy cycles performance enhance indicator (note) data output MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 35 figure 19. page program (pp) sequence (command 02) figure 20. 4 x i/o page program (4pp) sequence (command 38) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command 20 21 17 16 12 8 4 0 13 9 5 1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 21 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 22 18 14 10 6 2 23 19 15 11 7 3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# si/sio0 so/sio1 nc/sio3 wp#/sio2 38 command 10 11 12 13 14 15 16 17 18 19 20 21 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 36 figure 21. sector erase (se) sequence (command 20) figure 22. block erase (be) sequence (command d8) note: se command is 20(hex). note: be command is d8(hex). 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8 command figure 23. chip erase (ce) sequence (command 60 or c7) note: ce command is 60(hex) or c7(hex). 21 34567 0 60 or c7 sclk si cs# command MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 37 figure 24. deep power-down (dp) sequence (command b9) figure 25. rdp and read electronic signature (res) sequence (command ab) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 38 notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. (2) instruction is either 90(hex) or ef(hex) or df(hex). figure 26. release from deep power-down (rdp) sequence (command ab) figure 27. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so x 90 high-z command MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 39 figure 28. power-up timing note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. the parameter is characterized only. table 11. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 200 us MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 40 notes: 1. the value is guaranteed by characterization, not 100% tested in production. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 5 500000 us/v operating conditions at device power-up and power-down ac timing illustrated in figure 29 and figure 30 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 29. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 41 figure 30. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 42 erase and programming performance notes: 1. t ypical program and erase time assumes the following conditions: 25 c, 3.3v, and checker board pattern. 2. under worst conditions of 85 c and 2.7v . 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. latch-up characteristics parameter min. typ. (1) max. (2) unit write status register cycle time 40 100 ms sector erase cycle time 40 200 ms block erase cycle time 0.4 2 s chip erase cycle time 5 20 s byte program time (via page program command) 9 50 us page program cycle time 0.6 3 ms erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. data retention parameter condition min. max. unit data retention 55?c 20 years MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 43 ordering information part no. clock (mhz) temperature package remark MX25L1633Ezni-10g 104 -40 c~85 c 8-wson (6x5mm) rohs compliant MX25L1633Ezui-10g 104 -40 c~85 c 8-uson (4x4mm) rohs compliant MX25L1633Em2i-10g 104 -40 c~85 c 8-sop (200mil) rohs compliant MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 44 part name description mx 25 l 10 zn i g option: g: rohs compliant speed: 10: 104mhz temperature range: i: industrial (-40c to 85c) package: zn: 6mm x 5mm wson zu: 4mm x 4mm uson m2: 200mil 8-sop density & mode: 1633e: 16mb standard type type: l: 3v device: 25: serial flash 1633e MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 45 package information MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 46 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 47 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 48 revision history revision no. description page date 0.01 1. added 4 x i/o=80mhz @vcc=3.0v~3.6v p5, 27, 28 jun/21/2010 2. revised storage temperature p25 0.02 1. changed title from "advanced information " to "preliminary" p5 aug/02/2010 1.0 1. changed clock rate p5, 27, 28 aug/31/2010 2 x i/o read = from 75 mhz to 85mhz 4 x i/o read = from 75 mhz to 85mhz 2. removed 16 pin sop p6, 8, 43, 44 3. removed the title "preliminary" p5 1.1 1. changed tvr(min.) from 20us/v to 5us/v p40 nov/18/2010 2. modifed description for rohs compliance p6,43,44 1.2 1. updated 4pp program frequency p21,28 apr/26/201 1 1.3 1. revised tclqv spec from 10ns@30pf lo ading to 9ns@30pf loading. p28 jun/14/201 1 1.4 1. modifed wel bit description p16 aug/08/2012 2. modifed test conditions of ilo p27 1.5 1. added 8-uson 4x4mm package solution p6,8,43,44, nov/08/2012 p46 1.6 1. modifed tclqx spec. in ac characteristics table p28 dec/12/2012 1.7 1. removed advanced information from MX25L1633Ezui-10g p43 jan/09/2013 1.8 1. updated par ameters for dc characteristics. p5,27 nov/08/2013 2. updated era se and programming performance. p5,27~28,42 3. updated pac kage information p45~46 4. updated feature descriptions p5 MX25L1633E p/n: pm1581 rev. 1.8, nov. 08, 2013 MX25L1633E 49 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2010~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com |
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